0.2nm Process Technology to Be Achieved Within 15 Years

The Korean Semiconductor Engineers Association has released its "2026 Semiconductor Technology Roadmap," outlining predictions for the development of silicon-based semiconductor technology over the next 15 years. While Samsung recently launched the world’s first 2-nanometer Gate-All-Around (GAA) chip—the Exynos 2600—the roadmap forecasts that semiconductor circuit processes will advance to 0.2 nanometers by 2040, officially entering the ångström-scale (Å) technology era. However, over the next 15 years, the industry will need to overcome numerous challenges to achieve sub-1-nanometer wafer processes, as the path ahead remains long and arduous.  

According to ETNews, the core objective of this technology roadmap is to enhance long-term technological and industrial competitiveness in the semiconductor field, promote the practical application of academic research, and improve talent cultivation systems. The roadmap focuses on nine key technology directions: semiconductor devices and manufacturing processes, artificial intelligence semiconductors, optical interconnect semiconductors, wireless connectivity sensor semiconductors, wired connectivity semiconductors, power integrated circuit modules (PI M), chip packaging technology, and quantum computing.  

As reported by IT Home, Samsung's 2-nanometer GAA technology currently represents the highest level of lithography processes globally. It is reported that this Korean tech giant is already planning iterative upgrades for this process, having completed the foundational design for the second-generation 2-nanometer GAA process node and aiming to implement the third-generation 2-nanometer GAA technology—SF2P+—within two years. The roadmap notes that by 2040, the 0.2-nanometer process will adopt a complementary field-effect transistor (CFET) architecture and be paired with a monolithic 3D chip design.  

As a leading company in South Korea’s next-generation semiconductor manufacturing sector, Samsung has established a dedicated team to initiate research and development for 1-nanometer chips, with the goal of achieving mass production by 2029. These technological breakthroughs will not only be applied to system-on-chips (SoCs) for mobile devices but will also advance the memory chip sector. For DRAM, circuit processes will shrink from the current 11 nanometers to 6 nanometers, while high-bandwidth memory (HBM) is expected to undergo a leap in development, advancing from the current 12-layer stacking and 2TB/s bandwidth to 30-layer stacking and 128TB/s bandwidth.  

In the field of NAND flash memory, SK Hynix has already developed 321-layer stacked QLC technology. The roadmap predicts that the industry will achieve 2,000-layer stacked QLC NAND flash memory in the future. Additionally, current AI processors offer computational power of up to 10 TOPS (trillion operations per second), while the roadmap anticipates a significant leap in AI chip performance over the next 15 years: chips for model training are projected to reach 1,000 TOPS, and those for inference tasks are expected to achieve 100 TOPS.